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8 7
32.768KHZ 1TJS125DJ4A420P
1
CONN@ ACES_50611-0040N-001
R483 C481 22P_0402_50V8J TPM_XTALO U18
1 2
2 2
10K_0402_5%
2
LPC_LAD0
26
LAD0
LPC_LAD1
23
LAD1 25mA
LPC_LAD2 5mA
Change R481 to no 20
LAD2
+3VS +3VS
R488 LPC_LAD3 TPM_GPIO
17 6 PAD T76
D32 LAD3 GPIO
install. 11/30
220K_0402_1% LPC_LFRAME# TPM_GPIO2
22 2 PAD T77
LFRAME# GPIO2
USB20_N10 USB20_P10 PLT_RST#
1 2 3 2 16 Base I/O Address
16 FPR_OFF
IO2 IO1 LRESET#
+3VS
R481 @ 10K_0402_5% SUS_STAT# 0 = 02Eh
1 2 28
LPCPD#
Add on 11/15. SIRQ 1 =* 04Eh R482
4 1 27
+5VALW
PWR GND SERIRQ
C484 CLK_PCI_TPM_PCH 4.7K_0402_5%
21
LCLK
+USB20_N1_PWR CM1293A-02SR_SOT143-4 @ 10P_0402_50V8K
R484 R485
SLB 9635 T T 1.2
1 2 1 2 @ 10_0402_5%
@ 4.7K_0402_5% R486 0_0402_5%
15 8 1 2
15,31,32,33 PM_CLKRUN# CLKRUN# TEST1
9
TESTB1/BADD
R509
7
PP
@ 470_0402_5%
Have internal PD, 3 R487
NC
TPM_XTALO @4.7K_0402_5%
14 12
del R489. 11/30 XTALO NC
1
D NC
TPM_XTALI
13
XTALI/32K IN
Q65
2
G @ 2N7002_SOT23-3
S
SLB 9635 TT 1.2_TSSOP28
Change net name. 11/30
C C
SUS_STAT#
15,32,33 SUS_STAT#
Removed R490 connect to U3. 10/27
CLK_PCI_TPM_PCH
16 CLK_PCI_TPM_PCH
BIOS ROM(8MB)
+3VL
SPI_CLK R145 0_0402_5%
1 2
LPC Debug Port
+3VL
SPI ROM Socket Install on DB2.
1 Change from B+.
20mils
EMI request close to
1209
C485 U19 &U1
U19/34. 12/11
0.1U_0402_16V4Z
8 4
2 VCC VSS
Vin_Debug
R492
SPI_WP# SPI ROM 100K_0402_5%
3 Connect pin3 &
W
23. 11/11
20mils R493 3.3K_0402_5% SPI_HOLD#_1
1 2 7
+3VL
HOLD
45@ SST25VF032B-66_SO8
SPI_CS0#
1
31 SPI_CS0#
S
R6 @100K_0402_5% 8051_RECOVER# JDBG1
1 2
+3VL
SPI_CLK R494
6 1
31 SPI_CLK
C GND
33_0402_5%
Add R6. 4/23 2
16 CLK_PCI_DB_PCH LPC_PCI_CLK
SPI_SI SPI_SO_R
5 2 1 2 3
31 SPI_SI SPI_SO 31 GND
D Q
Add & Change. 11/11 4
13,24,31,33 LPC_LFRAME# LPC_FRAME#
B B
WIESO_G6179-100000_8P SIRQ
5
13,31,32,33 SIRQ
+3VS
6
4,13,16,21,22,24,27,30 PLT_RST#
LPC_RESET#
7
16,31,32 PCI_SERR# +3VS
Reserve for 8M rom not ready 12/02. 8
13,24,31,33 LPC_LAD0
LPC_AD0
9
13,24,31,33 LPC_LAD1
LPC_AD1
10
13,24,31,33 LPC_LAD2
LPC_AD2
11
13,24,31,33 LPC_LAD3
LPC_AD3
SPI ROM Socket 12
VCC_3VA
13
31 8051TX
PWR_LED#
U34
14
31 8051RX CAPS_LED#
SPI_HOLD#_1 SPI_CLK &U2
1 16 15
1 16 31 8051_RECOVER# NUM_LED#
SPI_SI
2 15 16
+3VL 39 DEBUG_KBCRST
2 15 VCC1_PWRGD
SPI_CLK_JP
3 14 17
3 14 SPI_CLK
SPI ROM SPI_CS0#_JP
4 13 18
4 13 SPI_CS#
SPI_SI_JP
5 12 19
5 12 SPI_SI
SPI_SO_JP
6 11 20
6 11 SPI_SO
SPI_CS0# 45@ SST25VF032B-66_SO8 21
SPI_HOLD#_0
7 10
7 10 SPI_HOLD#
SPI_SO_R SPI_WP#
8 9 22
31 SPI_CS1#
8 9 RSV
23
RSV
WIESO_G6179-07000002-00
Modify. 12/05 24
RSV
Colay 16 pins SPI ROM 25
GND
26
GND
CONN@ ACES_50238-02471-001
Removed R500, R501 connect to U3. 10/27
A A
SPI_HOLD#_1 R497 0_0402_5% SPI_HOLD#_0
1 2
SPI_CLK R498 0_0402_5% SPI_CLK_JP
1 2
SPI_SI R499 0_0402_5% SPI_SI_JP R495 3.3K_0402_5% SPI_WP# R496 0_0402_5%
1 2 1 2 1 2@
+3VL
20mils
Security Classification Compal Secret Data
SPI_CS0# R502 0_0402_5% SPI_CS0#_JP Compal Electronics, Inc.
1 2
2008/09/15 2009/09/15 Title
Issued Date Deciphered Date
SPI_SO_R R503 0_0402_5% SPI_SO_JP
1 2
TCG/BIOS ROM/PS2/SW LPC DEBUG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4951P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, July 28, 2009 Sheet 28 of 48
5 4 3 2 1
http://hobi-elektronika.net
C477
0.1U_0402_16V4Z
C478
0.1U_0402_16V4Z
C479
0.1U_0402_16V4Z
C480
0.1U_0402_16V4Z
S
D
C482
0.1U_0402_16V4Z
C483
10U_0805_10V4Z
0.1U_0402_16V4Z
G
C238
C705
2
2
1
24
19
10
5
VSB
VDD
VDD
VDD
1
2
2
1
2
1
2
1
3
1
2
1
GND
GND
GND
GND
4
25
18
11
2
1
@
47P_0402_50V8J
2
1
DOCKING CONNECTOR (190 pins) R_DOCK_RED C486 @0.1U_0402_16V4Z
1 2
Place close to R506 ~ R508. 11/11
R_DOCK_GRN C487 @0.1U_0402_16V4Z
1 2
DOCK_RED R520 @ 150_0402_1% DOCK_RED C516 @ 0.1U_0402_10V6K
2 1 1 2
VIN VA
(2) PS/2 Interfaces DOCK_GRN R521 @ 150_0402_1% DOCK_GRN C517 @ 0.1U_0402_10V6K R_DOCK_BLU C488 @0.1U_0402_16V4Z
2 1 1 2 1 2
(2) USB 2.channels DOCK_BLU R522 @ 150_0402_1% DOCK_BLU C518 @ 0.1U_0402_10V6K
2 1 1 2
(2) SATA Channels
(2) Display Port Channels
(1) Serial Port
L1
(1) Parallel Port
JDOCK1B
1 2
(1) Line In
HCB2012KF-121T50_0805 JDOCK1A
(1) Line Out
L18 12A DCAD DCAD2
143 46
T84 PAD PAD T85
(1) RJ45 (10/100/1000) 143 46
1 2 190 189 142 47
T87 PAD PAD T88
P1 G1 (1) VGA 142 47
HCB2012KF-121T50_0805
141 48
(1) 2 LAN indicator LED's 21 DPB_HPD 141 48 DPC_HPD 21
R504 1K_0402_5%
2 1 140 49
(1) Power Button 15 SLP_S5# ON/OFF# 25
140 49
139 50
(1) I2C interface ADP_SIGNAL
139 50
DPB_AUX R736 0_0402_5% DPB_DDC2CLK DPC_DDC6CLK R738 0_0402_5% DPC_AUX
1 1 188 1 1 2 138 51 1 2
188 1 138 51
DPB_AUX# R737 0_0402_5% DPB_DDC2DATA DPC_DDC6DATA R739 0_0402_5% DPC_AUX#
187 2 1 2 137 52 1 2
23 MDO3+ 187 2 MDO1+ 23 137 52
186 3 136 53 1
23 MDO3- 186 3 MDO1- 23 136 53
R505
185 4 Add on 12/10. 135 54 Add on 12/10.
2 2 185 4 135 54
1K_0402_5%
184 5 134 55
23 MDO2+ 184 5 MDO0+ 23 134 55
183 6 133 56
23 MDO2- 183 6 MDO0- 23 133 56 2
182 7 132 57
182 7 132 57
131 58
33 LPTSTB# D_DDCDATA 19
131 58
+5VS
130 59
33 LPTAFD# D_DDCCLK 19
130 59
DETECT
EMI request. 11/24 181 8 129 60
LED_LINK_LAN_DOCK# 23 33 LPTERR# D_VSYNC 19
181 8 129 60
180 9 Change. 0223 128 61
LAN_ACT# 22,23 33 LPTACK# D_HSYNC 19
180 9 128 61
179 10 127 62
+5VS 33 LPTBUSY
179 10 127 62
R_DOCK_RED R506 0_0402_5% DOCK_RED
178 11 126 63 1 2
VA +5VS 33 LPTPE
178 11 126 63
177 12 125 64
33 LPTSLCT
177 12 125 64
R_DOCK_GRN R507 0_0402_5% DOCK_GRN
Add. 0224 176 13 1 1 1 1 124 65 1 2
176 13 33 LPD7 124 65
Add. 0224 R_DOCK_BLU R508 0_0402_5% DOCK_BLU
175 14 123 66 1 2
175 14 33 LPD6 123 66
174 15 122 67
174 15 33 LPD5 122 67
173 16 121 68
33 LPD4
173 16 2 2 2 2 121 68 DCD#1 33 [ Pobierz całość w formacie PDF ]